In recent years, as the number of elements formed on one chip of a semiconductor integrated circuit increases, the rise in power consumption has become even a bigger issue. In order to solve this problem, methods in which a circuit area is defined for a circuit block that realizes each function, and then the operation clock is stopped or is decreased the frequency for each of the circuit area, and the power supply voltage is lowered for each of the circuit area so as to reduce power consumption during operation are proposed. In these methods, the power supply voltage and the operation clock frequency might be different for each circuit area.
In general, a FIFO buffer circuit is used to perform data transfer between areas having different operation clocks. For instance, there is a method in which a buffer is disposed across two operation clock areas, and the control circuit on the write side of the buffer is included in an input side area and the control circuit on the read side of the buffer is included in an output side area (refer to Patent Document 1).
The aforementioned buffer transfers data to the other area using a synchronous circuit that uses D-FF (D-Flip-Flop) circuits in two stages so that data transfer between the clocks of both the input side area and the output side area is performed accurately.
Various kinds of FIFO buffer circuits other than the one described have been developed, and data transfer between different operation clock areas is not unusual anymore.
Data transfer using a conventional FIFO buffer circuit is performed as shown in FIG. 25. The FIFO buffer circuit 7 performs data transfer between a logic area (A) 5 and a logic area (B) 6 operating at different operation clocks. Input data are written by giving the input data that should be transferred from the logic area (A) 5 to a data input 103 of the FIFO buffer circuit 7 and validating a write enable signal 102.
The FIFO buffer circuit 7 has a plurality of entries defined, and when all the entries have valid data written to them and are full, the FIFO buffer circuit 7 informs the logic area (A) 5 that the entries are full by returning a full signal 107 to the logic area (A) 5. When a piece of valid data is registered in the FIFO buffer circuit 7, it informs the logic area (B) 6 of the entry by invalidating an empty signal 106.
When a circuit in the logic area (B) 6 requests data by validating a read request signal 104, the data is obtained from a data output 105. Both an input side area clock 100 and an output side area clock 101 are supplied to the FIFO buffer circuit 7, which transmits data without any loss by switching the clock inside.
On the other hand, data transfer between areas operating at different power supply voltages is generally performed by a voltage level converting circuit. Data transfer between areas having different power supply voltages and operation clock frequencies can be achieved by having a FIFO buffer circuit and a voltage level converting circuit in series as shown in FIG. 26. In FIG. 26, the logic area (A) 5 has a power supply voltage of VDD1 and operates at an operation clock frequency of CLKI100 and the logic area (B) 6 has a power supply voltage of VDD2 and operates at an operation clock frequency of CLKO101.
When data transfer is performed between these areas, a FIFO buffer circuit 7′ temporarily synchronizes the clock of the output side area to the clock of the input side area and a voltage level converting circuit 8 matches the voltage level to VDD2. Then data is sent to the logic area (B) 6. The voltage level converting circuit 8 matches the voltage levels of output data 105′ and an empty signal 106′ of the FIFO buffer circuit 7′ to VDD2 and matches the voltage levels of the request signal 104 and the output side area clock 101 to VDD1.
In another method shown in FIG. 27, first the voltage level converting circuit 8 matches the voltage levels of the data input 103 and the write enable signal 102 from the logic area (A) 5, and the input side area clock 100 to VDD2 and then a FIFO buffer circuit 7′ performs data transfer between the areas operating at different clocks. The voltage level of the full signal from the FIFO buffer circuit 7″ is matched to VDD1 by the voltage level converting circuit 8.
In the cases of the circuit configurations shown in FIGS. 26 and 27 where data transfer between areas operating at different clock frequency is performed by the FIFO buffer circuit and then voltage conversion is performed by the voltage level converting circuit, a small circuit area such as an intermediate area 3 having the power supply voltage VDD1 and an operation clock 101′, obtained by converting the voltage level of the output side area clock 101, or an intermediate area 3′ having the power supply voltage VDD2 and an operation clock 100′, obtained by converting the voltage level of the input side area clock 100, is necessary between the voltage level converting circuit and the FIFO buffer circuit.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2004-295819A (FIGS. 1 and 2)
The disclosure of Patent Document 1 is incorporated in the present document by reference thereto.